Patent Cases, SYNOPSYS, INC., Plaintiff, v. REAL INTENT, INC., Defendant., U.S. District Court, N.D. California, (Aug. 10, 2026)

P. Casey Pitts, District Judge

ORDER GRANTING MOTION TO DISMISS IN PART

In this patent-infringement case, plaintiff Synopsys, Inc. alleges that defendant Real Intent, Inc. infringed claims of nine asserted patents concerning electronic design automation (EDA) software used to design and test (or “verify”) integrated circuits (ICs). Real Intent now moves to dismiss four of the claims in Synopsys's amended complaint under Federal Rule of Civil Procedure 12(b)(6), arguing that the asserted patents underlying those claims are subject-matter ineligible under 35 U.S.C. §101. For the reasons below, the Court grants the motion in part.

LEGAL STANDARD

I. Federal Rule of Civil Procedure 12(b)(6)

When considering a motion to dismiss an action for failure to state a claim under Rule 12(b)(6), the Court must “accept all factual allegations in the complaint as true and construe the pleadings in the light most favorable” to the non-moving party. Rowe v. Educ. Credit Mgmt. Corp., 559 F.3d 1028, 1029–30 (9th Cir. 2009) (quoting Knievel v. ESPN, 393 F.3d 1068, 1072 (9th Cir. 2005)). The pleadings must allege facts that allow the Court “to draw the reasonable inference that the defendant is liable for the misconduct alleged.” Ashcroft v. Iqbal, 556 U.S. 662, 678 (2009). Legal conclusions “can provide the framework of a complaint,” but the Court will not assume they are correct unless adequately “supported by factual allegations.” Id. at 679.

“[I]n many cases it is possible and proper to determine patent eligibility under 35 U.S.C. §101 on a Rule 12(b)(6) motion.” Genetic Techs. Ltd. v. Merial LLC, 818 F.3d 1369, 1373 (Fed. Cir. 2016). However, “plausible factual allegations may preclude dismissing a case under §101 where, for example, nothing on the record refutes those allegations as a matter of law or justifies dismissal under Rule 12(b)(6).” Aatrix Software, Inc. v. Green Shades Software, Inc., 882 F.3d 1121, 1125 (Fed. Cir. 2018); accord Cooperative Ent., Inc. v. Kollective Tech., Inc., 50 F.4th 127, 130 (Fed. Cir. 2022). “If there are claim construction disputes at the Rule 12(b)(6) stage,” the Court “must proceed by adopting the non-moving party's constructions,” or the Court “must resolve the disputes to whatever extent is needed to conduct the §101 analysis, which may well be less than a full, formal claim construction.” Aatrix Software, 882 F.3d at 1125. Neither party contends that any claim construction is required to resolve this motion.

II. 35 U.S.C. §101

Section 101 of the Patent Act makes patentable “any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof[.]” 35 U.S.C. §101. But that broad provision has an important exception: “Laws of nature, natural phenomena, and abstract ideas are not patentable.” Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 216 (2014).

In Alice, the Supreme Court established a two-step framework for assessing the validity of patent claims under §101. See id. At step one, the Court must “determine whether the claims at issue are directed to a patent-ineligible concept,” including abstract ideas, natural phenomena, or laws of nature. Id. at 218. “[S]tep one of the Alice framework does not require an evaluation of the prior art or facts outside of the intrinsic record regarding the state of the art at the time of the invention.” CardioNet, LLC v. InfoBionic, Inc., 955 F.3d 1358, 1374 (Fed. Cir. 2020). While the patent “specification [is] helpful in illuminating what a claim is ‘directed to’” at step one, “reliance on the specification must always yield to the claim language in identifying that focus.” ChargePoint, Inc. v. SemaConnect, Inc., 920 F.3d 759, 766 (Fed. Cir. 2019). “If the claims are not directed to a patent-ineligible concept under Alice step 1, ‘the claims satisfy §101 and [the Court] need not proceed to the second step.’” Data Engine Techs. LLC v. Google LLC, 906 F.3d 999, 1007 (Fed. Cir. 2018) (quoting Core Wireless Licensing S.A.R.L. v. LG Elecs., Inc., 880 F.3d 1356, 1361 (Fed. Cir. 2018)). “[C]ourts commonly find ‘functional’ claims—i.e., those that recite a result without providing details for how that result is to be achieved—to be directed to abstract ideas. Further, the fact that a claimed step can be performed by the human mind or a person with a pencil and paper has often been found to be an indication that the claims are directed to patent ineligible abstract ideas.” Skillz Platform Inc. v. Aviagames Inc., No. 21-CV-02436-BLF, 2022 WL 783338, at *6 (N.D. Cal. Mar. 14, 2022) (collecting cases).

At Alice step two, the Court “search[es] for an ‘inventive concept’—i.e., an element or combination of elements that is sufficient to ensure that the patent in practice amounts to significantly more than a patent upon the ineligible concept itself.” Alice, 573 U.S. at 217–18 (citation modified). “Deciding whether claims recite an ‘inventive concept,’ or something more than ‘well-understood, routine, conventional activities previously known to the industry,’ may turn on underlying ‘question[s] of fact.’” Skillz Platform Inc., 2022 WL 783338, at *6 (first quoting Aatrix Software, Inc. v. Green Shades Software, Inc., 882 F.3d 1121, 1128 (Fed. Cir. 2018); and then quoting Alice, 573 U.S. at 217–18). “If a claim's only ‘inventive concept’ is the application of an abstract idea using conventional and well-understood techniques, the claim has not been transformed into a patent-eligible application of an abstract idea.” Id. (first quoting BSG Tech LLC v. Buyseasons, Inc., 899 F.3d 1281, 1290–91 (Fed. Cir. 2018); and then citing Content Extraction and Transmission LLC v. Wells Fargo Bank, Nat. Ass'n, 776 F.3d 1343, 1347–48 (Fed. Cir. 2014)).

“In cases involving software innovations, the Alice step two and frequently the Alice step one inquiry ‘often turns on whether the claims focus on specific asserted improvements in computer capabilities or instead on a process or system that qualifies an abstract idea for which computers are invoked merely as a tool.’” Id. at *7 (quoting Uniloc USA, Inc. v. LG Electronics USA, Inc., 957 F.3d 1303, 1306–07 (Fed. Cir. 2020)). “‘[S]oftware can make patent-eligible improvements to computer technology, and related claims are eligible as long as they are directed to non-abstract improvements to the functionality of a computer or network platform itself.’” Id. (first quoting Uniloc, 957 F.3d at 1309; and then citing Customedia Techs., LLC v. Dish Net. Corp., 951 F.3d 1359, 1365 (Fed. Cir. 2020)). “The Federal Circuit has found software-related claims eligible where (1) ‘the claimed advance is on a solution to a problem specifically arising in the realm of computer networks or computers,’ and (2) ‘the claim is properly characterized as identifying a specific improvement in computer capabilities or network functionality, rather than only claiming a desirable result or function.’” Id. (quoting TecSec, Inc. v. Adobe Inc., 978 F.3d 1278, 1293 (Fed. Cir. 2020)) (cleaned up). “The improvement need not be defined by reference to ‘physical components.’” Id. (first citing Uniloc, 957 F.3d at 1309; and then citing Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1339 (Fed. Cir. 2016) (“To hold otherwise risks resurrecting a bright-line machine-or-transformation test … or creating a categorical ban on software patents.”)). But “the Federal Circuit has stated that software patents are invalid where they ‘merely recite generalized steps to be performed on a computer using conventional computer activity.’” Id. (first quoting Uniloc, 957 F.3d at 1308; and then citing BASCOM Glob. Internet Servs., Inc. v. AT&T Mobility LLC, 827 F.3d 1341, 1350 (Fed. Cir. 2016) (noting that claims would be invalid if they “merely recite[d] the abstract idea … along with the requirement to perform it on the Internet, or to perform it on a set of generic computer components”)).

“In determining whether claims are directed to a patent-eligible improved computer system rather than an abstract idea, courts have found that technical advantages described in the specification can be a significant indication of eligibility.” Id. at *7 (first citing CardioNet, 955 F.3d at 1369–70 (noting that advantages disclosed in the patent specification are “important in our determination that the claims are drawn to a technological improvement”); and then citing Visual Memory LLC v. NVIDIA Corp., 867 F.3d 1253, 1259–60 (Fed. Cir. 2017)). But technological details set forth only in the specification, and not in the patents' claims, cannot supply an inventive concept. See Intell. Ventures I LLC v. Symantec Corp., 838 F.3d 1307, 1322 (Fed. Cir. 2016) (“The district court erred in relying on technological details set forth in the patent's specification and not set forth in the claims to find an inventive concept.”). “Courts also consider the prosecution history to be relevant to assessing whether the claims are directed to an improvement in computer technology.” Skillz Platform Inc., 2022 WL 783338, at *7 (citing Ancora Techs., Inc. v. HTC America, Inc., 908 F.3d 1343, 1348–49 (Fed. Cir. 2018)). “And courts also must consider factual allegations in the [c]omplaint.” Id. (citing Aatrix, 882 F.3d at 1125).

Patent eligibility “may be resolved at the Rule 12 stage only if there are no plausible factual disputes after drawing all reasonable inferences from the intrinsic and Rule 12 record in favor of the non-movant.” Cooperative Ent., Inc. v. Kollective Tech., Inc., 50 F.4th 127, 130 (Fed. Cir. 2022). “If there are claim construction disputes at the Rule 12(b)(6) stage,” the Court “must proceed by adopting the non-moving party's constructions,” or the Court “must resolve the disputes to whatever extent is needed to conduct the §101 analysis, which may well be less than a full, formal claim construction.” Aatrix, 882 F.3d at 1125 (citation modified).

ANALYSIS

I. The ′773 Patent

Real Intent first moves to dismiss Synopsys's claim for infringement of U.S. Patent No. 10,289,773. As the amended complaint explains, the ′773 patent presents a method for identifying potentially redundant circuitry—specifically, “isolation gates.” Dkt. No. 28 ¶¶63–64. “Isolation gates are circuit elements used particularly in IC designs with multiple power domains and/or reset domains” and serve primarily “to prevent the propagation of undefined or unwanted signals between these domains when one domain is powered down or in a reset state, while the other domain is active.” Id. ¶64. Traditionally, circuit designers used separate circuitry (including isolation gates) to handle reset domain crossings (“RDCs”) and power domain crossings (“PDCs”). Id. ¶63. The former are typically mapped using a Hardware Description Language (HDL) description, while the latter are typically mapped using a Unified Power Format (“UPF)” description. See Dkt. No. 28-5 at 2 (′773 patent). According to the ′773 patent and the amended complaint, the use of separate isolation gates for RDCs and PDCs resulted in redundant circuitry, thereby producing “unnecessarily larger circuit designs and signal delays.” Dkt. No. 28 ¶63; see also Dkt. No. 28-5 at 2–3. The ′773 patent describes a method of comparing HDL descriptions of RDCs and UPF descriptions of PDCs to identify and report areas in a circuit design where RDCs and PDCs overlap—that is, areas with potentially redundant circuitry. Dkt. No. 28 ¶¶63 – 68; Dkt. No. 28-5 at 16–17. The method aims to enable circuit designers to eliminate redundancies by using shared isolation gates for overlapping RDCs and PDCs. The amended complaint alleges that “[f]ewer isolation gates lead to reduced signal delays, improving overall circuit speed,” and “improves the overall verification process, reducing the risk of metastability issues.” Dkt. No. 28 ¶67; see also Dkt. No. 28-5 at 1.

Claim 1 of the ′773 patent recites:

A method of efficiently addressing reset domain crossings (RDCs) and power domain crossings (PDCs) in an initial circuit design, said initial circuit design including a plurality of circuit structures and a plurality of signals passing between said plurality of circuit structures, said initial circuit design being defined by an initial Hardware Description Language (HDL) description in which each of said plurality of circuit structures is assigned to an associated reset domain of a plurality of reset domains such that one or more of said plurality of signals forms a corresponding said RDC between two reset domains of said plurality of reset domains, said initial circuit design being further defined by an initial Unified Power Format (UPF) description in which each of said plurality of circuit structures is further assigned to an associated power domain of a plurality of power domains such that one or more of said plurality of signals forms a corresponding said PDC between two power domains of said plurality of power domains, the method comprising:

utilizing both said initial HDL description and said initial UPF description to identify at least one signal of said plurality of signals that forms both a corresponding said RDC and a corresponding said PDC;

generating a report indicating that said at least one signal is a candidate for a shared RDC/PDC isolation structure.

Dkt. No. 28-5 at 16–17.

At Alice step one, claim 1 of the ′773 patent addresses an abstract idea. As noted above, the patent itself states that RDCs and PDCs were commonly used in ICs prior to the ′773 patent and are typically mapped using HDL and UPF descriptions, respectively. So claim 1's only contribution is a comparison of the two and the reporting of identified overlaps. “In other words,” as Real Intent argues, “this claim simply takes the abstract idea of set intersection and applies it to well-understood techniques for identifying RDCs and PDCs using conventional … circuit descriptions.” Dkt. No. 39 at 5. “[T]he Federal Circuit has generally found claims abstract where they are directed to some combination of acquiring information, analyzing information, or displaying the results of that analysis.” Enovsys LLC v. Uber Techs., Inc., No. 23-CV-04549-EJD, 2024 WL 3033995, at *5 (N.D. Cal. June 17, 2024) (collecting cases).

Synopsys argues that claim 1 of the ′773 patent is not directed to an abstract idea because it “does not recite a generic process for identifying overlaps between two sets of information.” Instead, Synopsys continues, claim 1 specifically requires the comparison of HDL descriptions of RDCs and UPF descriptions of PDCs to identify and report candidates for shared RDC/PDC isolation gates—a narrowly defined application of the broader set-intersection idea, and one that can only be performed on a computer given that HDL and UPF descriptions are “computer code.” Dkt. No. 52 at 5. But the Supreme Court made clear in Alice that neither requiring the use of a computer nor “limiting the use of an abstract idea to a particular technological environment” can “transform a patent-ineligible abstract idea into a patent-eligible invention.” 573 U.S. at 223. Synopsys fails to identify any “non-abstract improvements to the functionality of a computer … itself” that result from the method recited in claim 1 of the ′773 patent. Skillz Platform Inc., 2022 WL 783338, at *7 (citation modified). For example, unlike the patent at issue in Finjan, Inc. v. Blue Coat Systems, Inc., on which Synopsys relies, claim 1 of the ′773 patent does not describe the creation of any “new kind of file.” 879 F.3d 1299, 1304–05 (Fed. Cir. 2018). Claim 1 simply recites the comparison of two admittedly common file-types (HDL and UPF) to “generat[e] a report” of unspecified format that identifies overlaps. See Koninklijke KPN N.V. v. Gemalto M2M GmbH, 942 F.3d 1143, 1150 (Fed. Cir. 2019) (explaining that patent-eligible claims must “receipt a specific means or method” of achieving the desired result, not just the result itself)

At Alice step two, claim 1 of the ′773 patent contains no inventive concept. As just discussed, claim 1 offers no “specific asserted improvements in computer capabilities.” Skillz Platform Inc., 2022 WL 783338, at *7 (citation modified). Synopsys contends that its proposed use of HDL and UPF descriptions is inventive because such descriptions are conventionally used to map RDCs and PDCs separately, not to identify potential isolation circuitry that could be shared for both. To the contrary, claim 1 uses HDL and UPF descriptions for their usual purposes of mapping RDCs and PDCs; claim 1 then adds the step of comparing those two typical outputs to identify overlapping isolation gates. That is nothing more than “the application of an abstract idea [i.e., comparing two common sets of information to reduce redundancies] using conventional and well-understood techniques.” Id. at *6 (citation modified). Indeed, given the patent's admission that HDL and UPF descriptions are the typical formats used to depict RDCs and PDCs, it is difficult to imagine how a provider of EDA software might otherwise propose to compare RDC and PDC circuitry. And beyond its generalized instruction to “utiliz[e]” the typical formats for depicting RDC and PDC circuitry, claim 1 never describes with specificity how to compare RDCs and PDCs or report identified overlaps. Accordingly, all the alleged benefits from claim 1 of the ′773 patent concern general improvements to a circuit design that would result from any identification and elimination of redundant RDC and PDC circuitry, rather than specific technical improvements to EDA software from the use of a particular method of comparing RDCs and PDCs. See Dkt. No. 28 ¶67 (“improving circuit performance by eliminating signal delays generated by redundant isolation gates” and “improving overall circuit speed”). So these benefits are not “significantly more than the abstract idea” of comparison “itself” and cannot supply “[a]n inventive concept that transforms the abstract idea into a patent-eligible invention[.]” BASCOM, 827 F.3d at 1349.

The analysis does not meaningfully differ for the remaining asserted claims of the ′773 patent. [1] The only other independent claim is Claim 11, which proposes the even more abstract idea of “utilizing a [UPF] description of the circuit design and a [HDL] description of the circuit design to identify at least one signal that forms a [RDC] … and also forms a [PDC] …” All the other asserted claims depend from claims 1 or 11 and merely add already-intuitive instructions that would be necessary for virtually any comparison of RDC and PDC isolation circuitry—e.g., checking whether a signal present in the HDL description of the RDC is also present in the UPF description of the PDC (cl. 2 and 14), seeing whether corresponding signals are each associated with isolation resources (cl. 3, 5, and 15), and “generating a report” of the findings (cl. 12).

The Court therefore grants Real Intent's motion to dismiss Synopsys's claim for infringement of the ′773 patent.

II. The ′948 Patent

Real Intent also moves to dismiss Synopsys's claim for infringement of U.S. Patent No. 9,529,948. The ′948 patent describes a method for more efficiently verifying “crossover paths” in an IC design, which are “signal path[s] … that cross[] from one power domain [in the circuit] to another” and are typically mapped using UPF descriptions. Dkt. No. 28 ¶69; see also Dkt. No. 28-6 at 1–2, 7. Almost all modern silicon chips have multiple power (or “voltage”) states—for example, a high-power state that ensures maximum performance at the cost of higher power consumption and a low-power state that reduces power consumption at the cost of lower performance. Dkt. No. 28-6 at 1. Different power domains within an IC operate at different power states, with some domains being switched off in certain states. Id. In prior methods for verifying crossover paths, IC designers would “verify[] that the circuit paths function correctly for all possible combinations of voltage states for each power domain.” Id. But some of those combinations might “not occur during operation of the final circuit,” making analysis of crossover paths for those combinations “unnecessary” and potentially “misleading to users” if it indicated functional errors that would not affect the circuit's operation. Id. The ′948 patent proposes an approach for avoiding such unnecessary (and expensive) analysis by limiting verification to crossover paths that are actually used in a final IC's operation. Specifically, the patent teaches a method of limiting verification to a subset of crossover paths identified in a UPF description as functioning in the IC's low-power state. Id. at 1–2; Dkt. No. 28 ¶¶70–71. According to the amended complaint, “[b]y analyzing a smaller set of paths, the overall verification time is significantly reduced because there are fewer paths to analyze, thereby lowering computational demands of verification.” Dkt. No. 28 ¶72.

Claim 1 of the ′948 patent recites:

A method for functional verification of a circuit description utilizing a power design description, the method comprising:

generating a first set of crossover paths based on the circuit description;

generating a low power information based on the power design description being associated with the circuit description, the low power information determining a set of power state combinations;

generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths; and

evaluating each of the second set of crossover path

Dkt. No. 28-6 at 10–12.

Like the ′773 patent, the ′948 patent addresses patent-ineligible subject matter.

At Alice step one, claim 1 of the ′948 patent is directed to the abstract idea of filtering out unused crossover paths from circuit verification. The claim is extremely light on detail, offering only four steps defined by functional language: (1) “generating” a first set of crossover paths for the whole circuit, (2) “generating” a description of the circuit in a low-power state, (3) “generating” a second set of crossover paths based on the overlap between the first set and the low-power state description, and (4) “evaluating” that second set. As one court in this district previously characterized another Synopsys patent that used similarly general and functional language, “[t]he claim does not explain or lay out a specific way or inventive technology for performing these steps. At its core, what the claim language describes is a method of discarding irrelevant information and retaining a sub-set of desired relevant information. This is a typical mental process that humans regularly perform and as such, is not patent eligible.” Synopsys, Inc. v. Avatar Integrated Sys., Inc., No. 20-CV-04151-WHO, 2020 WL 6684853, at *6 (N.D. Cal. Nov. 12, 2020), order clarified, No. 20-CV-04151-WHO, 2020 WL 7626427 (N.D. Cal. Dec. 22, 2020). Claims using such functional language are frequently held to be directed to abstract ideas. See Skillz Platform, 2022 WL 783338, at *6.

Synopsys argues that claim 1 is not directed to an abstract idea because the steps it recites “are particular to computer-implemented circuit verification tools.” Dkt. No. 52 at 12. But as explained above, neither the use of a computer nor the limitation of a claimed method to a particular technological environment transforms an abstract idea into a non-abstract one.

Synopsys also analogizes claim 1 of the ′948 patent to one of the subject-matter eligible claims asserted in Data Engine Techs. LLC v. Google LLC, 906 F.3d 999 (Fed. Cir. 2018). The analogy fails. The claim in Data Engine concerned the now-familiar use of “tabs” to navigate three-dimensional spreadsheets, providing a “highly intuitive, user-friendly interface” that replaced the burdensome and complicated prior methods of operating such spreadsheets. Id. at 1008. The Federal Circuit held that the claim was not directed to an abstract idea because it proposed a “particular way” of solving a “known technological problem.” Id. Synopsys latches onto this language, asserting that claim 1 of the ′948 patent similarly solves a known technological problem (the inefficiency and expense of verifying every crossover path in an IC design) in a particular way (filtering the crossover paths to be verified based on what is used a circuit's low-power state). But claim 1 here provides nowhere near the level of detail that was present in the claim in Data Engine, which:

Recite[d] specific steps detailing the method of navigating through spreadsheet pages within a three-dimensional spreadsheet environment using notebook tabs. The claim require[d] displaying on a screen display a row of spreadsheet page identifiers along one side of the first spreadsheet page, with each spreadsheet page identifier being a notebook tab. The claim require[d] at least one user-settable identifying character to label the notebook tab and describe[d] navigating through the various spreadsheet pages through selection of the notebook tabs. The claim further require[d] a formula that uses the identifying character to operate on information spread between different spreadsheet pages that are identified by their tabs.

Id. Here, by contrast, claim 1 offers no “specific … implementation,” id. at 1009, and instead recites generic results-oriented steps of “generating” datasets without describing how. For that reason, claim 1 is directed to an abstract idea.

At Alice step two, claim 1 of the ′948 patent contains no inventive concept. The ′948 patent makes clear that almost all the individual steps recited in claim 1—i.e., generating sets of crossover paths, creating low-power state descriptions, and verifying crossover-path sets—were known in the prior art and commonly practiced before the ′948 patent issued. The contribution of claim 1 of the ′948 patent is merely the cross-referencing of a crossover-path set with a low-power state description to generate a narrower crossover-path set for verification. Synopsys contends that this filtering “leads to faster, more efficient, and resource-conscious verification, ultimately contributing to accelerated IC design cycles” and “avoid[ing] unnecessary analysis of crossover paths that will not be active during the resulting chip's operation.” Dkt. No. 28 ¶¶74–75. But achieving the purported benefits of claim 1 “require[s] no improved computer resources [Synopsys] claims to have invented, just already available computers, with their already available basic functions, to use as tools in executing the claimed process.” SAP Am., Inc. v. InvestPic, LLC, 898 F.3d 1161, 1169–70 (Fed. Cir. 2018). “[C]laiming the improved speed or efficiency inherent with applying the abstract idea on a computer” cannot “provide a sufficient inventive concept.” Intell. Ventures I LLC v. Cap. One Bank (USA), 792 F.3d 1363, 1367 (Fed. Cir. 2015). As Real Intent argues, the only purported benefit of claim 1 that does not stem from the inherent speed and efficiency of using a computer derives from “the abstract idea itself: narrowing a larger set of paths into a smaller set for evaluation.” Dkt. No. 57 at 7. “[A] claimed invention's use of the ineligible concept to which it is directed cannot supply the inventive concept that renders the invention ‘significantly more’ than that ineligible concept.” BSG Tech LLC v. Buyseasons, Inc., 899 F.3d 1281, 1290 (Fed. Cir. 2018).

The additional asserted claims of the ′948, all of which depend from claim 1, fare no better. Claims 2 and 6 add additional criteria for filtering crossover paths, but claim 2 does not explain how to determine which paths meet its criteria, and claim 6 simply requires that some of the crossover paths are of a particular type, thereby merely narrowing a still-abstract idea. Claims 11 and 12 propose the use of unspecified parameters and rules when evaluating crossover paths, again without specifying how to do so. None of this narrowing transforms the core abstract idea underlying the patent. See SAP, 898 F.3d at 1169. Claim 13 merely proposes “displaying” identified errors. See Elec. Power Grp., LLC v. Alstom S.A., 830 F.3d 1350, 1354–55 (Fed. Cir. 2016) (displaying information is abstract). And claims 14 and 15 provide for filtering either using “static analysis” or “without simulation.” While the ′948 patent's specification and the amended complaint state that claim 14 and 15's eschewal of any simulation other than a static analysis differentiates those claims' recited methods from “conventional approaches,” Dkt. No. 28; Dkt. No. 28-6 at 2, neither the specification nor the amended complaint suggest that filtering without simulation or using only static analysis were newly invented computer functions. See SAP, 898 F.3d at 1169 (holding that the addition of claims specifying the use of particular existing methods does not transform an abstract idea). Thus, while the allegations in the complaint may plausibly show the novelty of claim 14 and 15's approach, they do not establish inventiveness. See Affinity Labs of Texas, LLC v. DIRECTV, LLC, 838 F.3d 1253, 1263 (Fed. Cir. 2016) (explaining that these are separate inquiries).

Accordingly, the Court grants Real Intent's motion to dismiss as to the ′948 patent.

III. The ′173 Patent

Real Intent next moves to dismiss Synopsys's claim for infringement of U.S. Patent No. 8,607,173. The ′173 patent proposes a “method for performing hierarchical bottom-up clock-domain crossing verification.” Dkt. No. 28 ¶28. Clock-domain crossing (CDC) verification is a test used to verify certain aspects of a circuit design:

In modern computer chip designs, a single chip often contains circuits that operate at different clock speeds. When signals from one part of the chip are transmitted to another part of the chip that is running at a different clock speed, there may be errors that lead to chip failure if the signals aren't “synchronized.” CDC verification is the step in the design process where engineers identify and correct those errors and has become an essential part of chip design flows.

Synopsys, Inc. v. Real Intent, Inc., No. 5:20-CV-02819-EJD, 2023 WL 3047381, at *1 (N.D. Cal. Apr. 21, 2023). Due to the increasing size and complexity of IC designs, the time and complexity of CDC verification has also increased. See Dkt. No. 28 ¶28; Dkt. No. 28-1 at 1–2. The ′173 patent describes a method to make CDC verification runs more efficient by obviating the need to verify the entirety of an IC model in detail. Specifically, the ′173 patent proposes an approach to CDC verification in which individual modules within an IC design are verified and then replaced with an abstraction that provides only a clock domain for the module's input and output. See Dkt. No. 28 ¶29; Dkt. No. 28-1 at 1–2. The proposed approach is “bottom-up” and iterative, first replacing the smallest and lowest-level modules within a design with an abstraction, and then replacing groups of those low-level abstractions with single higher-level abstractions, and so on. See Dkt. No. 28 ¶30; Dkt. No. 28-1 at 3. Prior to the ′173 patent, CDC verification involved either “time-consuming verification runs of an entire IC design, hiding the details of IP blocks in the design and/or partitioning the design into blocks, which often resulted in incomplete verification results.” Dkt. No. 28 ¶30; see also Dkt. No. 28-1 at 1. But when using a simplified IC model created with the abstractions proposed by the ′173 patent, designers can run “repeated verification cycles without the high burden associated with repeated runs at the system-on-chip (SoC) level [or] incomplete results with IP Block constraints.” Dkt. No. 28 ¶30; see also Dkt. No. 28-1 at 3.

Claim 1 of the ′173 patent recites:

A method for clock-domain crossing (CDC) verification of a model of an integrated circuit (IC) comprising a plurality of modules, the method comprising:

identifying a module from among the plurality of modules that has not been previously abstracted or that has not changed since a previous abstraction, the module having an input and an output;

performing a CDC verification on the module in a bottom up fashion by a computer processor device;

replacing the module with a corresponding abstraction module that correctly identifies a corresponding clock domain for each of the input and the output, the replacing performed in response to the module successfully passing the respective CDC verification;

repeating the identifying, performing, and replacing for each of the remaining modules from among the plurality of modules; and

storing an updated model of the IC comprising at least a replaced module in storage.

Dkt. No. 28-1 at 8.

Once again, the asserted claims of the ′173 patent are directed to a patent-ineligible idea.

At Alice step one, claim 1 of the ′173 patent addresses an abstract idea: using abstractions to break up analysis into more manageable parts. As Real Intent argues, courts in this district have often found such task-management methods to be patent-ineligible. See, e.g., Coho Licensing LLC v. Glam Media, Inc., 2017 WL 6210882, at *5 (N.D. Cal. Jan. 23, 2017), aff'd sub nom. Coho Licensing LLC v. Oath Inc., 710 F. App'x 892 (Fed. Cir. 2018); Avatar, 2020 WL 6684853, at *1. Indeed, another court in this district held a similar Synopsis patent ineligible in Avatar. The asserted claim there “describe[d] a method of creating a block abstraction that involves processing at least one of the blocks in a hierarchically decomposed circuit wherein said processing includes retaining only a sub-set of information about the block, … and then utilizing said abstraction in another development phase.” 2020 WL 6684853, at *6 (citation modified). The Avatar court concluded that, notwithstanding its technical language, the claim was directed to an abstract idea:

The claim does not explain or lay out a specific way or inventive technology for performing these steps. At its core, what the claim language describes is a method of discarding irrelevant information and retaining a sub-set of desired relevant information. This is a typical mental process that humans regularly perform and as such, is not patent eligible. The Federal Circuit has routinely found that collecting information “including when limited to particular content (which does not change its character as information), as within the realm of abstract ideas.” Electric Power Group, LLC v. Alstom S.A., 830 F.3d 1350 (Fed. Cir. 2016). The method described in the … patent of discarding irrelevant information and retaining a sub-set of specific information is just another way that humans regularly sort and analyze information and is equally abstract.

Id. (citation modified). The same analysis applies here.

So too does Avatar's rejection of the same counter-arguments Synopsys asserts here—namely, that the claim is not directed to an abstract idea because it purports to propose a technical improvement specific to the context of designing circuits on computer:

Synopsys argues that the patent claims are not abstract because they are directed to a specific method “for use in hierarchical integrated circuit design.” While this does narrow the claim, being narrowed or cabined to a particular industry or process does not make an abstract concept concrete. … Synopsys argues that the … patent claims are not abstract because they involve an “inventive data structure [that] represents an improvement in hierarchical decomposition in that it addresses a specific drawback identified by the inventors with preexisting methods.” … But what Synopsys characterizes as an “inventive data structure” here is just data. The … patent is clear that … abstractions are conventionally used in computer chip design.

See id. at *6–7.

Synopsys contends that, unlike the claim at issue in Avatar, the abstraction called for by claim 1 of the ′173 patent involves creating an entirely new data structure that captures different and more detailed information than was captured by abstractions in the prior art. If true, that might constitute the sort of “non-abstract improvement[] to computer technology” that could satisfy Alice step one. Finjan, 879 F.3d at 1304 (quoting Enfish, 822 F.3d at 1335–36). In Finjan, for example, the Federal Circuit held that a claim was not directed to an abstract idea where its recited method for virus scanning described how to create an entirely new type of file by taking an existing “downloadable” (i.e., “an executable application program” that “is downloaded from a source computer and run on the destination computer”) and “attach[ing] the results of [a virus] scan to the downloadable itself in the form of a ‘security profile’” that contained specified content about the “potentially hostile or suspicious code operations that may be attempted by the [d]ownloadable.” Id. at 1303–04 (citation modified). But unlike in Finjan, neither the claim language nor the complaint describes how a new data structure containing the contemplated abstraction is to be created—the claim merely calls for the result of “replacing the [existing] module with a corresponding abstraction module” containing certain information. Such “result-based functional language” fails to “sufficiently describe how to achieve the[]” replacement of the existing module “in a non-abstract way.” Two-Way Media Ltd. v. Comcast Cable Commc'ns, LLC, 874 F.3d 1329, 1337 (Fed. Cir. 2017).

At Alice step two, claim 1 of the ′173 patent contains no inventive concept. Synopsys does not assert that any component step in its claimed process is unconventional or unknown—to the contrary, it notes that prior art disclosed processes of abstraction and verification. Rather, Synopsys claims that claim 1's particular sequencing of those steps is unconventional and reaps significant efficiency gains. But as discussed above with respect to the ′773 and ′948 patents, those purported benefits inhere in the abstract idea of distributed processing and breaking up tasks, so it does not constitute something significantly more than the abstract idea itself. And the claim is “not tied to a specific structure” and uses purely functional language that does not prescribe a particular technical improvement to the functioning of EDA software or a computer. See Avatar, 2020 WL 6684853, at *8.

Again, the analysis does not meaningfully change for the other asserted claims of the ′173 patent. Claim 2 depends from claim 1 and adds a requirement that “the abstraction model includes an assumption for the input of the module and a constraint for an output port of the output of the module.” Claim 4 depends from claim 2, adding another requirement that the aforementioned constraint “comprises at least one of module name, port name, clock domain, name of at least one of synchronizers, flip-flops (FFs), and latches.” And claim 5 depends from claim 4, specifying that “the constraint is an indication that there is a synchronizer within the clock domain of the output port.” These claims merely narrow the still-abstract idea of distributed processing by adding assumptions and constraints, without proposing specific technical improvements.

Accordingly, the Court grants Real Intent's motion to dismiss as to Synopsys's claim for infringement of the ′173 patent.

IV. The ′560 Patent

Finally, Real Intent moves to dismiss Synopsys's claim for infringement of U.S. Patent No. 8,359,560. The ′560 patent describes a method “for debugging [IC] designs.” Dkt. No. 28-4 at 1. As the amended complaint explains:

When designing integrated circuits, designers often work at the RTL level …, and then use a synthesis tool to convert their design to the gate level. … However, many design issues, such as manual design changes, timing optimizations, and postsynthesis debugging, can only be discovered at the gate level. As circuit designs became increasingly complex, debugging and tracing signals between two different design levels became a “technological bottleneck in the chip design industry.”

Dkt. No. 28 ¶57 (quoting Dkt. No. 28-4 at 1). The ′560 patent “addresses that technological bottleneck by enabling the synchronous debugging of an IC design at both the RTL level and the gate level.” Id. ¶58. The proposed method does so by presenting multiple debugging process simultaneously in separate windows, “each corresponding to a design level (e.g., RTL level or gate level).” Id. When a user interacts with a signal in one window, the user can drag and drop that signal into the other window, “allow[ing] IC designers to ‘browse and trace the two design levels at the same time, thus significantly reducing the debugging time for complex designs.’” Id. (quoting Dkt. No. 28-4 at 1).

Claim 1 of the ′560 patent recites:

A computer-implemented method for debugging designs, comprising:

obtaining signal correlation information for signals of a design at least two design levels, by using a computer, loading and presenting design descriptions corresponding to the design at the at least two design levels in at least two sets of windows, by using the computer;

receiving a selection of a first signal in a first set of windows, by using the computer;

in response to the selection of the first signal, querying a second signal corresponding to the first signal according to the signal correlation information, so as to select the second signal in a second set of windows, by using the computer;

executing at least two debugging processes, by using the computer, each responsible for loading one of the design descriptions at the at least two design levels, and each in control of one of the at least two sets of windows for debugging the loaded design, wherein each debugging process has a plurality of windows;

receiving a drag of the first signal from a first window in a first debugging process to a second window in a second debugging process, by using the computer;

and in response to a synchronization information comprising the drag of the first signal, locating the second signal in the second window in the second debugging process, by using the computer.

Dkt. No. 28-4 at 8.

Unlike the other patents challenged by Real Intent's motion, claim 1 of the ′560 patent is not directed to an abstract idea. This claim primarily concerns the display of IC debugging processes through a graphic user interface (GUI). As the parties recognize, the key question in §101 challenges to patents concerning GUIs is whether the claim “describe[s] a specific structure improving the interface itself.” Broadband iTV, Inc. v. Amazon.com, Inc., No. 20-cv-00921, 2022 WL 4703425, at *13 (W.D. Tex. 2022) (collecting cases). Where a claim merely proposes a process of displaying information without “any particular assertedly inventive technology for performing those functions,” it is “directed to an abstract idea.” Elec. Power Grp., 830 F.3d at 1354; see also AI Visualize, Inc. v. Nuance Commc'ns, Inc., 97 F.4th 1371, 1379 (Fed. Cir. 2024) (“creation” of virtual visualization of existing dataset, “recited in general terms, [wa]s abstract data manipulation”); Hawk Tech. Sys., LLC v. Castle Retail, LLC, 60 F.4th 1349, 1352, 1357 (Fed. Cir. 2023) (concluding that claim proposing a method to transmit and display videos while conserving bandwidth was abstract where the claims did not “describe how the alleged goal of conserving bandwidth … is achieved”).

Here, claim 1 of the ′560 patent does more than merely recite its goal (enabling simultaneous debugging at multiple levels) or call generically for the display of information (debugging processes) using conventional or unspecified methods. Instead, claim 1 proposes a concrete method for its simultaneous-debugging goal: displaying two debugging processes in separate windows that a user can synchronize by dragging a selected signal from one window to the other. Thus, “the claim[] focus[es] on a specific means or method that improves the relevant technology,” Apple, Inc. v. Ameranth, 842 F.3d 1229, 1241 (Fed. Cir. 2016), which the patent represents previously required more labor-intensive sequential debugging.

Core Wireless Licensing S.A.R.L. v. LG Elecs., Inc., 880 F.3d 1356 (Fed. Cir. 2018), is instructive. There, the Federal Circuit held that asserted claims were not abstract where they were “directed to a particular manner of summarizing and presenting information in electronic devices” that optimized the user interface of devices “with small screens.” Id. at 1362. The Federal Circuit explained that, just as the ′560 patent asserts that single-window debugging displays had restricted efficient debugging across multiple levels, the “prior art interfaces” in Core Wireless “had many deficits relating to the efficient functioning of the computer” because they “requir[ed] a user to scroll around and switch views many times,” a process that “could seem slow, complex and difficult to learn.” Id. at 1363 (citation modified).

Like the claimed invention in Core Wireless, the method proposed in claim 1 of the′560 patent “improves the efficiency of using” the patentee's product, and the improvement (multiple windows showing multiple debugging processes) is a “specific” change from prior art (using one window to show one debugging process at a time). To be sure, the claim here is less detailed than the claim at issue in Core Wireless and uses pre-existing technologies, as the underlying debugging processes and ability to display those processes were not novel. But the Federal Circuit has made clear that an “inventive concept can be found in the non-conventional and non-generic arrangement of known, conventional pieces.” BASCOM, 827 F.3d at 1350. For that reason, claim 1 of the ′560 patent at least plausibly satisfies Alice. At this stage, that is all that is required.

Because claim 1 is not directed to an abstract idea, it passes muster on that basis, and the Court need not continue to Alice step two. But the Court notes for the parties' benefit that claim 1 also plausibly contains an inventive concept that could satisfy step two. Real Intent argues otherwise based on its view that the use of two windows to display simultaneous debugging processes “merely recite[s] generalized steps to be performed on a computer using conventional computer activity.'” Skillz Platform Inc., 2022 WL 783338, at *7 (citation modified). But as described above, both the patent and the amended complaint assert that the use of multiple windows in this arena is far from “conventional” and is instead a significant departure from past practices of debugging each level separately.

The analysis does not differ for claim 5 of ′560 patent, the only other asserted claim. Real Intent argues that claim 5 is subject-matter ineligible only because it depends from and does not materially change the abstractness or inventiveness of claim 1. So Real Intent's arguments as to claim 5 fails for the reasons just discussed.

Real Intent's motion to dismiss Synopsys's claim for infringement of the ′560 patent is therefore denied.

CONCLUSION

For the foregoing reasons, the asserted claims of the ′773, ′948, and ′173 patents are subject-matter ineligible on their face under 35 U.S.C. §101. Real Intent's motion to dismiss Synopsys's claims for infringement of those patents is therefore GRANTED. Because Synopsys has already amended its complaint in response to Real Intent's arguments concerning the patents' subject-matter eligibility, and because “[n]o [further] amendment … would cure the validity problems with the underlying patents,” dismissal is with prejudice and without leave to amend. See Semiconductor Design Techs., LLC v. Cadence Design Sys., Inc., 735 F. Supp. 3d 1162, 1169 (N.D. Cal. 2024) (citing Sanderling Mgmt. Ltd. v. Snap Inc., 65 F.4th 698, 706 (Fed. Cir. 2023).

Real Intent's motion to dismiss Synopsys's claim for infringement of the ′560 patent is DENIED.

IT IS SO ORDERED.