IP Law Daily, PATENT—Fed. Cir.: Micron preserves PTAB obviousness wins over memory-module patent claims, (Sep 3, 2026)

By Saurabh Kashyap, B.A., M.A., LL.B., LL.M.

Prior art supported the Board’s findings that claimed memory-module features, including selectively enabled data paths, on-module voltage regulation, and reduced-load stacked-memory connections, would have been obvious.

The U.S. Court of Appeals for the Federal Circuit has affirmed Patent Trial and Appeal Board (PTAB) decisions finding claims of five Netlist, Inc. patents covering related computer-memory technologies unpatentable as obvious. In three decisions issued the same day, the court rejected Netlist’s challenges to findings involving memory-module data buffers, voltage regulation, and three-dimensional stacked-memory architecture. The court’s precedential decision involving U.S. Patent No. 10,949,339 (the ’339 patent) led the trio, holding that substantial evidence supported findings that prior art taught selectively enabling buffer data paths according to a latency parameter (Netlist, Inc. v. Micron Technology, Inc, No. 24-1707 (Fed. Cir. Sep. 2, 2026); Netlist, Inc. v. Micron Technology, Inc., Nos. 24-1859 and 24-1863 (Fed. Cir. Sep. 2, 2026); and Netlist, Inc. v. Micron Technology, Inc., Nos. 24-2240 and 24-2241 (Fed. Cir. Sep. 2, 2026)).

Memory technology. Netlist develops memory and storage technologies, while Micron Technology, Inc. and its affiliates manufacture semiconductor and memory products. The disputes arose from inter partes reviews originally pursued by Samsung Electronics Co., Ltd., with Micron later filing petitions challenging the same claims on the same prior-art theories. Samsung subsequently settled with Netlist and withdrew from the appeals, leaving Micron as the appellee.

The precedential appeal concerned the ’339 patent, directed to improving the performance and capacity of memory boards containing dual in-line memory modules, or DIMMs. The technology places buffers between a memory controller and dynamic random-access memory (DRAM) devices. Those buffers contain data paths that ordinarily remain disabled, electrically isolating the DRAM devices from the memory controller, but are selectively enabled during read or write operations.

The Board found claims 1-35 obvious over Ellsberry, a published patent application describing memory modules using memory-bank switches to selectively connect memory banks to data buses, alone or in combination with Halbert, a patent describing memory-module circuitry using bidirectional tristate buffers. On appeal, Netlist principally disputed whether Ellsberry taught enabling a data path according to a latency parameter and whether it disclosed enabling the claimed data path at all.

Buffer timing. The Federal Circuit found substantial evidence supporting the Board. Ellsberry taught memory-bank switches, mapped to the claimed buffers, containing ports whose data paths could be enabled and disabled. It also disclosed storing a “Posted CAS_n” latency parameter in the memory-bank switch. Together with applicable Joint Electron Device Engineering Council (JEDEC) standards addressing read and write latency, that evidence supported the finding that Ellsberry used latency information to control when data paths were enabled.

Netlist argued that the Board improperly relied on Netlist’s own U.S. Patent No. 7,532,537 (the ’537 patent), which was not asserted as a reference in the petition, to establish that adding a clock cycle for propagation delay through a buffer. Under SAS Institute Inc. v. Iancu, 584 U.S. 357 (2018), an IPR must proceed according to the grounds presented in the petition rather than on grounds devised by the Board.

The Federal Circuit did not decide whether the Board improperly expanded the role of the ’537 patent because any error was harmless. Alternatively, the Board found that Ellsberry itself taught adding one clock cycle to account for propagation delay through its switch ASICs, and expert testimony provided substantial evidence for that finding.

The court also rejected Netlist’s contention that Ellsberry merely enabled memory banks rather than data paths within the buffer. Ellsberry placed Ports A and B within its switch ASIC and described activating one port while disabling another. Its bidirectional drivers supported the Board’s conclusion that enabling the ports enabled corresponding data paths. Halbert provided additional support through tristate buffers capable of enabling and disabling data paths. The Board’s reasoning was also sufficiently discernible to satisfy the Administrative Procedure Act.

Voltage regulation. In a separate nonprecedential decision, the Federal Circuit affirmed findings that all challenged claims of U.S. Patent Nos. 11,016,918 (the ’918 patent) and 11,232,054 (the ’054 patent) were obvious. Those patents concern memory modules containing on-module voltage converters that receive power from a host system and generate regulated voltages for components mounted on the module.

The Board relied principally on Harris, a published patent application describing memory modules with on-module voltage regulation, combined with JEDEC Fully Buffered Dual In-Line Memory Module (FBDIMM) standards governing memory-module architecture, including delivery of power through module edge connections. The Federal Circuit rejected Netlist’s argument that the Board departed from the petitions by relying on the combined teachings to show host-system power delivered through those connections. The petitions fairly presented the combination, and substantial evidence showed that FBDIMMs conventionally received power from the host system through their edge connectors.

Substantial evidence also supported using multiple converters to generate the required regulated voltages. Harris contemplated on-module voltage regulation, while the FBDIMM standards identified multiple required voltage rails. Expert testimony identified practical reasons for separate converters, including independent power control, reduced noise coupling, cost savings, and space considerations.

For dependent claims addressing voltage monitoring, the Board additionally relied on Amidi, a patent describing circuitry for detecting abnormal voltage conditions and initiating protective action. The Board reasonably found that Amidi’s disclosure of “power faults,” considered with expert evidence that overvoltage was a known danger, encompassed monitoring and responding to overvoltage. Because those findings supported obviousness, the Federal Circuit did not reach the Board’s alternative reliance on Hajeck.

Stacked memory. The third, also nonprecedential, decision concerned U.S. Patent Nos. 8,787,060 (the ’060 patent) and 9,318,160 (the ’160 patent), which share a specification and address reducing driver load in three-dimensional stacked memory packages. Stacking additional array dies increases memory capacity but also increases the electrical load that control-die drivers must overcome. Netlist’s patents sought to reduce that load by limiting the number of array dies connected to individual interconnects and reducing the length of some interconnects.

The obviousness grounds involved Kim, a published patent application describing stacked memory in which array dies connect to a control die through-silicon vias (TSVs). Rajan, a patent teaching groups of DRAM dies sharing a data bus. The Board also relied on Riho, which taught connecting array dies to a control die through TSVs, and Wyman, which disclosed that different-length TSVs impose different loads and described drivers capable of supplying different amounts of power.

The Federal Circuit upheld the Board’s finding that Kim and Rajan rendered the principal claims obvious. Combining their teachings was straightforward because Kim contemplated using additional dies and Rajan provided a way to connect multiple dies through a shared data bus. Using that approach could avoid additional TSVs that would consume more space and circuitry.

Netlist’s teaching-away argument failed because Kim’s disclosure of a one-to-one relationship between dies and interconnects did not criticize, discredit, or discourage connecting multiple dies to a single interconnect. Substantial evidence also supported the Board’s finding that skilled artisans knew how to address potential data collisions in the proposed combination.

The court additionally affirmed obviousness findings for dependent claims addressing electrical-load balancing and differently sized drivers. Riho supported the finding that load could be considered when grouping dies, while Wyman taught physically separate drivers capable of providing different amounts of signal drive. The court also rejected Netlist’s APA challenge to the Board’s treatment of undisputed limitations.

Accordingly, the Federal Circuit left intact the Board’s obviousness determinations across all five patents, with the ’339 patent ruling providing the only precedential decision among the three appeals.

The Cases are No. 24-1707; No. 24-1859; and No. 24-2240.

Judge: Reyna, J. Stark, L. Linn, R.

Attorneys: Jeffrey A. Lamken, Jennifer Elizabeth Fischell, and Rayiner Hashem, (MoloLamken LLP) for Netlist, Inc. Michael Rueckheim (King & Spalding LLP) for Micron Technology, Inc.

Companies: Netlist, Inc.; Micron Technology, Inc.

Cases: Patent FedCirNews